Anghel et al., 2007 - Google Patents
Multi-level fault effects evaluationAnghel et al., 2007
View HTML- Document ID
- 2785336867199686917
- Author
- Anghel L
- Rebaudengo M
- Reorda M
- Violante M
- Publication year
- Publication venue
- Radiation Effects on Embedded Systems
External Links
Snippet
The problem of analyzing the effects of transient faults in a digital system is very complex, and it may be addressed successfully only if it is performed at different steps of the design process. In this work we report and overview of fault injection, discussing which techniques …
- 230000000694 effects 0 title abstract description 35
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Nguyen et al. | Chip-level soft error estimation method | |
Nguyen et al. | A systematic approach to SER estimation and solutions | |
Rao et al. | Computing the soft error rate of a combinational logic circuit using parameterized descriptors | |
Mitra et al. | Logic soft errors in sub-65nm technologies design and CAD challenges | |
Rossi et al. | Multiple transient faults in logic: An issue for next generation ICs? | |
Cha et al. | A gate-level simulation environment for alpha-particle-induced transient faults | |
Seifert et al. | Timing vulnerability factors of sequentials | |
Mitra et al. | The resilience wall: Cross-layer solution strategies | |
Sterpone et al. | A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs | |
De Sio et al. | Radiation-induced Single Event Transient effects during the reconfiguration process of SRAM-based FPGAs | |
Kalbarczyk et al. | Hierarchical simulation approach to accurate fault modeling for system dependability evaluation | |
Gil et al. | Fault Injection into VHDL models: experimental validation of a fault-tolerant microcomputer system | |
Clark et al. | Modeling single-event effects in a complex digital device | |
Anghel et al. | Multi-level fault effects evaluation | |
Evans et al. | Case study of SEU effects in a network processor | |
Gil et al. | A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system | |
Kritikakou et al. | Flodam: Cross-layer reliability analysis flow for complex hardware designs | |
Zhao et al. | Soft-spot analysis: targeting compound noise effects in nanometer circuits | |
Grosso et al. | Exploiting fault model correlations to accelerate SEU sensitivity assessment | |
Kudva et al. | Fault injection verification of IBM POWER6 soft error resilience | |
Sootkaneung et al. | Gate input reconfiguration for combating soft errors in combinational circuits | |
Portolan et al. | Alternatives to fault injections for early safety/security evaluations | |
Ebrahimi et al. | Cross-layer approaches for soft error modeling and mitigation | |
Cannon et al. | Multiscale system modeling of single-event-induced faults in advanced node processors | |
Tajima et al. | A low power soft error hardened latch with schmitt-trigger-based C-Element |