Ho et al., 2009 - Google Patents
Nonvolatile memristor memory: Device characteristics and design implicationsHo et al., 2009
View PDF- Document ID
- 2306808025155448534
- Author
- Ho Y
- Huang G
- Li P
- Publication year
- Publication venue
- Proceedings of the 2009 International Conference on Computer-Aided Design
External Links
Snippet
The search for new nonvolatile universal memories is propelled by the need for pushing power-efficient nanocomputing to the next higher level. As a potential contender for the next- generation memory technology of choice, the recently found" the missing fourth circuit …
- 230000015654 memory 0 title abstract description 30
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Ho et al. | Nonvolatile memristor memory: Device characteristics and design implications | |
Ho et al. | Dynamical properties and design analysis for nonvolatile memristor memories | |
Chen et al. | Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design | |
Manem et al. | Design considerations for multilevel CMOS/nano memristive memory | |
Ebong et al. | Self-controlled writing and erasing in a memristor crossbar memory | |
Yilmaz et al. | A drift-tolerant read/write scheme for multilevel memristor memory | |
KR20090123244A (en) | Phase change memory device and write method thereof | |
Shaarawy et al. | Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM | |
CN105931665B (en) | Phase change memory reading circuit and method | |
Wald et al. | Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic | |
WO2015112164A1 (en) | Memristor memory | |
Zangeneh et al. | Performance and energy models for memristor-based 1T1R RRAM cell | |
Ramadan et al. | Adaptive programming in multi-level cell ReRAM | |
CN114868188B (en) | Counter-based reading in a memory device | |
Shaarawy et al. | 2T2M memristor-based memory cell for higher stability RRAM modules | |
US20160012884A1 (en) | Memory system and method of operation of the same | |
WO2009120691A1 (en) | Random access memory with cmos-compatible nonvolatile storage element | |
US9941003B2 (en) | Multi-level resistive memory structure | |
WO2016157719A1 (en) | Rewriting method for semiconductor storage apparatus, and semiconductor storage apparatus | |
Mohammad et al. | Hybrid Memristor-CMOS memory cell: Modeling and design | |
Giraud et al. | Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro | |
Ko et al. | Temperature-tracking sensing scheme with adaptive precharge and noise compensation scheme in PRAM | |
US8804434B2 (en) | Pulse-based memory read-out | |
Bagheri-Soulla et al. | An RRAM-based MLC design approach | |
Adhikari et al. | Memristance drift avoidance with charge bouncing for memristor-based nonvolatile memories |