Gao et al., 2019 - Google Patents
Low temperature Cu interconnect with chip to wafer hybrid bondingGao et al., 2019
View PDF- Document ID
- 2273678612179294842
- Author
- Gao G
- Mirkarimi L
- Workman T
- Fountain G
- Theil J
- Guevara G
- Liu P
- Lee B
- Mrozek P
- Huynh M
- Rudolph C
- Werner T
- Hanisch A
- Publication year
- Publication venue
- 2019 IEEE 69th Electronic Components and Technology Conference (ECTC)
External Links
Snippet
Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and …
- 238000000034 method 0 abstract description 66
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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