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Souriau et al., 2019 - Google Patents

Wafer Level Integration of Thin Silicon Bare Dies Within Flexible Label

Souriau et al., 2019

Document ID
2049428516547099966
Author
Souriau J
Itawi A
Castagné L
Publication year
Publication venue
2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

External Links

Snippet

This paper presents new developments on the integration of ultra-thin silicon bare dies within a flexible label made on wafer carrier. It is proposed to interconnect silicon die on an electrical network by flip-chip and to perform collective thinning using conventional …
Continue reading at ieeexplore.ieee.org (other versions)

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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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