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Gross, 1983 - Google Patents

Code optimization of pipeline constraints

Gross, 1983

Document ID
17833621439476488753
Author
Gross T
Publication year

External Links

Snippet

A pipelined processor divides the execution of an instruction over several independent units, called pipestages. Multiple instructions are executed concurrently; each instruction occupies a different pipestage. This organization creates hazards if an instruction needs the result …
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Classifications

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    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
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    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching
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    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
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