Nothing Special   »   [go: up one dir, main page]

Na et al., 2015 - Google Patents

An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM

Na et al., 2015

View PDF
Document ID
17403701683894242784
Author
Na T
Kim J
Song B
Kim J
Kang S
Jung S
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067Single-ended amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C14/00Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements using thin films in plane structure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store

Similar Documents

Publication Publication Date Title
Na et al. STT-MRAM sensing: a review
Salehi et al. Survey of STT-MRAM cell design strategies: Taxonomy and sense amplifier tradeoffs for resiliency
Maffitt et al. Design considerations for MRAM
Dong et al. A 1-Mb 28-nm 1T1MTJ STT-MRAM with single-cap offset-cancelled sense amplifier and in situ self-write-termination
Kim et al. Multilevel spin-orbit torque MRAMs
Sakimura et al. MRAM cell technology for over 500-MHz SoC
Bishnoi et al. Read disturb fault detection in STT-MRAM
Na et al. An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM
Bishnoi et al. Improving write performance for STT-MRAM
Na et al. Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM
JP3959417B2 (en) Semiconductor memory readout circuit
KR20150144037A (en) Memory core of resistive type memory device, resistive type memory device including the same and method of sensing data in resistive type memory device
Kang et al. Dynamic dual-reference sensing scheme for deep submicrometer STT-MRAM
KR20170024997A (en) Boosted voltage generator of resistive type memory device, voltage generator including the same and resistive type memory device including the same
Garzón et al. Exploiting STT-MRAMs for cryogenic non-volatile cache applications
CN105745716A (en) Offset canceling dual stage sensing circuit
Song et al. Latch offset cancellation sense amplifier for deep submicrometer STT-RAM
KR20150132360A (en) Mixed memory type hybrid cache
Kwon et al. High-density and robust STT-MRAM array through device/circuit/architecture interactions
KR20180049416A (en) Nonvolatile memory device and operating method thereof
Na et al. Read disturbance reduction technique for offset-canceling dual-stage sensing circuits in deep submicrometer STT-RAM
Xue et al. An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs
KR20170133072A (en) Resistive type memory device and integrated circuit including the same
Nehra et al. High-performance computing-in-memory architecture using STT-/SOT-based series triple-level cell MRAM
Na et al. Data-cell-variation-tolerant dual-mode sensing scheme for deep submicrometer STT-RAM