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Anjankar et al., 2016 - Google Patents

FPGA based multiple fault tolerant and recoverable technique using triple modular redundancy (FRTMR)

Anjankar et al., 2016

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Document ID
17346837508725018517
Author
Anjankar S
Kolte M
Pund A
Kolte P
Kumar A
Mankar P
Ambhore K
Publication year
Publication venue
Procedia computer science

External Links

Snippet

Abstract Triple Modular Redundancy (TMR) is real time reliability known to improve computing systems. This paper presents an approach towards the implementation of a fault tolerant FPGA based technique. Proposed scheme allows the diagnosis of transient and …
Continue reading at www.sciencedirect.com (PDF) (other versions)

Classifications

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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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