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Holländer et al., 2006 - Google Patents

Strain relaxation of pseudomorphic Si1− xGex/Si (1 0 0) heterostructures by Si+ ion implantation

Holländer et al., 2006

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Document ID
17157599848665598883
Author
Holländer B
Buca D
Mantl S
Herzog H
Hackbarth T
Loo R
Caymax M
Mörschbächer M
Fichtner P
et al.
Publication year
Publication venue
Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms

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Strain relaxation of pseudomorphic Si1− xGex layers (x= 0.21–0.33) grown by chemical vapor deposition or molecular-beam epitaxy on Si (100) or silicon-on-insulator was investigated after low-fluence Si+ ion implantation and annealing. Strain relaxation of up to …
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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