Viaud et al., 2006 - Google Patents
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principlesViaud et al., 2006
View PDF- Document ID
- 17143553171689060856
- Author
- Viaud E
- Pêcheux F
- Greiner A
- Publication year
- Publication venue
- Proceedings of the Design Automation & Test in Europe Conference
External Links
Snippet
The paper presents an innovative simulation scheme to speed-up simulations of multi- clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC …
- 238000004088 simulation 0 title abstract description 55
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Viaud et al. | An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles | |
Binkert et al. | The M5 simulator: Modeling networked systems | |
Ruaro et al. | Memphis: a framework for heterogeneous many-core SoCs generation and validation | |
Conte et al. | Multi-microprocessor systems for real-time applications | |
Beltrame et al. | Multi-accuracy power and performance transaction-level modeling | |
Atitallah et al. | An MPSoC performance estimation framework using transaction level modeling | |
Owda et al. | Trace-based simulation framework combining message-based and shared-memory interactions in a time-triggered platform | |
Roth et al. | Asynchronous parallel mpsoc simulation on the single-chip cloud computer | |
Cox | Ritsim: Distributed systemc simulation | |
Wild et al. | Performance evaluation for system-on-chip architectures using trace-based transaction level simulation | |
Khaligh et al. | Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs | |
Roth et al. | A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation | |
Hein et al. | RASSP virtual prototyping of DSP systems | |
Li et al. | Formal and virtual multi-level design space exploration | |
Beltrame et al. | Exploiting TLM and object introspection for system-level simulation | |
Lopes et al. | Chronos: An abstract NoC-based manycore with preserved temporal and spatial traffic distribution | |
Eggenberger et al. | Globally asynchronous locally synchronous simulation of nocs on many-core architectures | |
Roth et al. | A framework for exploration of parallel SystemC simulation on the single-chip cloud computer | |
Harbin et al. | Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip | |
Afzal et al. | Making applications faster by asynchronous execution: Slowing down processes or relaxing MPI collectives | |
Kim et al. | Software platform for hybrid resource management of a many-core accelerator for multimedia applications | |
Zhou et al. | Detailed and clock-driven simulation for HPC interconnection network | |
Grüttner et al. | Challenges of multi-and many-core architectures for electronic system-level design | |
Grigg et al. | Towards a scheduling and timing analysis solution for integrated modular avionic systems | |
Dasari | Timing Analysis of Real-Time Systems Considering the Contention on the Shared Interconnection Network in Multicores |