Nothing Special   »   [go: up one dir, main page]

Ebrahimi et al., 2014 - Google Patents

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Ebrahimi et al., 2014

View PDF
Document ID
16431979633757264813
Author
Ebrahimi M
Evans A
Tahoori M
Seyyedi R
Costenaro E
Alexandrescu D
Publication year
Publication venue
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)

External Links

Snippet

Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models all generation …
Continue reading at www.date-conference.com (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Similar Documents

Publication Publication Date Title
Ebrahimi et al. Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales
Ebrahimi et al. Comprehensive analysis of sequential and combinational soft errors in an embedded processor
Saggese et al. An experimental study of soft errors in microprocessors
Kwon et al. Razor-lite: A light-weight register for error detection by observing virtual supply rails
Mitra et al. Logic soft errors in sub-65nm technologies design and CAD challenges
Nguyen et al. Chip-level soft error estimation method
Fazeli et al. Soft error rate estimation of digital circuits in the presence of multiple event transients (METs)
George et al. Transient fault models and AVF estimation revisited
Herkersdorf et al. Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
Cho Impact of microarchitectural differences of RISC-V processor cores on soft error effects
Cho et al. System-level effects of soft errors in uncore components
Cho et al. Understanding soft errors in uncore components
Saggese et al. Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic
Kuentzer et al. Soft error detection and correction architecture for asynchronous bundled data designs
Yu et al. Efficient fault detection architecture design of latch-based low power DSP/MCU processor
Asadi et al. Soft error modeling and remediation techniques in ASIC designs
Kriebel et al. ACSEM: Accuracy-configurable fast soft error masking analysis in combinatorial circuits
Rao et al. A detailed characterization of errors in logic circuits due to single-event transients
Bouajila et al. An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft-and timing errors
Kritikakou et al. Flodam: Cross-layer reliability analysis flow for complex hardware designs
Pournaghdali et al. VHDLSFI: A simulation-based multi-bit fault injection for dependability analysis
Yuan et al. InTimeFix: A low-cost and scalable technique for in-situ timing error masking in logic circuits
Ebrahimi et al. Cross-layer approaches for soft error modeling and mitigation
Cheng Cross-layer resilience to tolerate hardware errors in digital systems
Paliaroutis et al. Placement-based SER estimation in the presence of multiple faults in combinational logic