Vo, 2017 - Google Patents
Implementing the on-chip backpropagation learning algorithm on FPGA architectureVo, 2017
- Document ID
- 15789706151130429258
- Author
- Vo H
- Publication year
- Publication venue
- 2017 International Conference on System Science and Engineering (ICSSE)
External Links
Snippet
Scaling CMOS integrated circuit technology leads to decrease the chip price and increase processing performance in complex applications with re-configurability. Thus, VLSI architecture is a promising candidate in implementing neural network models nowadays …
- 238000004422 calculation algorithm 0 title abstract description 24
Classifications
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- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/0635—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means using analogue means
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- G—PHYSICS
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- G06N3/082—Learning methods modifying the architecture, e.g. adding or deleting nodes or connections, pruning
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- G06N3/04—Architectures, e.g. interconnection topology
- G06N3/0472—Architectures, e.g. interconnection topology using probabilistic elements, e.g. p-rams, stochastic processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/10—Simulation on general purpose computers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- G06F17/5009—Computer-aided design using simulation
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
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- G06N3/12—Computer systems based on biological models using genetic models
- G06N3/126—Genetic algorithms, i.e. information processing using digital simulations of the genetic system
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- G06N99/00—Subject matter not provided for in other groups of this subclass
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
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