Nothing Special   »   [go: up one dir, main page]

Lingambudi et al., 2012 - Google Patents

A case study of high-speed serial interface simulation with IBIS-AMI models

Lingambudi et al., 2012

View PDF
Document ID
15605363592371472329
Author
Lingambudi A
Edlund G
Haridass A
Becker D
Publication year
Publication venue
2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

External Links

Snippet

High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems. These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing packet switching networks
    • H04L43/50—Testing arrangements

Similar Documents

Publication Publication Date Title
US8504334B2 (en) Simulating the transmission and simultaneous switching output noise of signals in a computer system
US10237097B2 (en) Worst case eye for multi-level pulse amplitude modulated links
US9058442B2 (en) Incorporating noise and/or jitter into waveform generation
US10726188B1 (en) Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface
Lingambudi et al. A case study of high-speed serial interface simulation with IBIS-AMI models
US20110137603A1 (en) Enforcing Worst-Case Behavior During Transmit Channel Analysis
Luo et al. Fast response prediction method based on bidirectional long short-term memory for high-speed links
US10467366B2 (en) Methods and systems for simulating high-speed link designs
Oh et al. Hybrid statistical link simulation technique
Chu et al. Simulink-based modeling and PCA-based nonlinearity evaluation for high-speed links
Cristofoli et al. Efficient statistical simulation of intersymbol interference and jitter in high-speed serial interfaces
US9178542B1 (en) Methods and apparatus for accurate transmitter simulation for link optimization
Chang et al. Jitter modeling in statistical link simulation
US8682621B2 (en) Simulating the transmission of asymmetric signals in a computer system
US10740506B2 (en) Statistical channel analysis with correlated multiple-level input modulation
Tsuk et al. An electrical-level superposed-edge approach to statistical serial link simulation
US10628624B1 (en) System and method for simulating channels using true strobe timing
Chu et al. Modeling for nonlinear high-speed links based on deep learning method
US9673862B1 (en) System and method of analyzing crosstalk without measuring aggressor signal
US7924911B2 (en) Techniques for simulating a decision feedback equalizer circuit
Chada et al. Improved transmitter jitter modeling for accurate bit error rate (BER) eye contours using transient simulation of short bit patterns
US9048941B2 (en) Characteristic response extraction for non-linear transmit channels
Oh et al. Prediction of system performance based on component jitter and noise budgets
US9177087B1 (en) Methods and apparatus for generating short length patterns that induce inter-symbol interference
Aydiner et al. Modeling of DDR5 signaling from jitter sequences to accurate bit error rate (BER)