Nothing Special   »   [go: up one dir, main page]

He et al., 2011 - Google Patents

A First-Principle Guided Circuit Simulator of Linear Complexity and its Linear Speedup for Die-Package Co-Design

He et al., 2011

Document ID
15521574145820841355
Author
He Q
Chen D
Jiao D
Publication year
Publication venue
International Electronic Packaging Technical Conference and Exhibition

External Links

Snippet

In this work, guided by electromagnetics-based first principles, we develop a circuit simulator that allows for the simulation of a circuit including both nonlinear devices and the linear network in linear complexity. Moreover, it permits an almost embarrassingly parallel …
Continue reading at asmedigitalcollection.asme.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861—Retrieval from the Internet, e.g. browsers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/04—CAD in a network environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/16—Numerical modeling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/82—Noise analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/80—Thermal analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/02—Component-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/84—Timing analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence

Similar Documents

Publication Publication Date Title
Ferranti et al. Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis
Raveloa Delay modeling of high-speed distributed interconnect for the signal integrity prediction
Bondarenko et al. Development of simple physics-based circuit macromodel from PEEC
He et al. From layout directly to simulation: A first-principle-guided circuit simulator of linear complexity and its efficient parallelization
Engin Efficient sensitivity calculations for optimization of power delivery network impedance
He et al. Fast electromagnetics-based co-simulation of linear network and nonlinear circuits for the analysis of high-speed integrated circuits
Zhai et al. The 2‐D boundary element techniques for capacitance extraction of nanometer VLSI interconnects
Kumashiro et al. Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures
Menshov et al. Surface–volume–surface electric field integral equation for magneto-quasi-static analysis of complex 3-D interconnects
Lee et al. From O (k 2 N) to O (N): A fast complex-valued eigenvalue solver for large-scale on-chip interconnect analysis
Roy et al. Macromodeling of multilayered power distribution networks based on multiconductor transmission line approach
Ugryumova Applications of model order reduction for IC modeling
Gala et al. Inductance model and analysis methodology for high-speed on-chip interconnect
Ma et al. Electrothermal modeling for 3-D nanoscale circuit substrates: Noise
He et al. A First-Principle Guided Circuit Simulator of Linear Complexity and its Linear Speedup for Die-Package Co-Design
He et al. Minimal-order circuit model based fast electromagnetic simulation
Hu et al. Fast on-chip inductance simulation using a precorrected-FFT method
Chen et al. A direct domain-decomposition-based time-domain finite-element method of linear complexity for simulating multiscaled structures in integrated circuit systems
Elfadel et al. A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis
Lee et al. Fast structure-aware direct time-domain finite-element solver for the analysis of large-scale on-chip circuits
Yu et al. Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
Chen et al. SuPREME: Substrate and power-delivery reluctance-enhanced macromodel evaluation
Romano et al. Anisotropic and optimized FFT-based iterative electromagnetic solver for the PEEC method
Sieiro et al. Synthesis of planar inductors in low temperature co-fired ceramic technology
Yu et al. The application of boundary element method to the resistance calculation problem in designing flat panel displays