Nothing Special   »   [go: up one dir, main page]

Huang et al., 2012 - Google Patents

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Huang et al., 2012

Document ID
15467766012998120673
Author
Huang Y
Li J
Chou C
Publication year
Publication venue
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test

External Links

Snippet

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318508Board Level Test, e.g. P1500 Standard
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318385Random or pseudo-random test pattern
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation

Similar Documents

Publication Publication Date Title
Huang et al. A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Karthick et al. A novel 3-D-IC test architecture-a review
CN115020266B (en) 2.5D chip bound test circuit
Huang et al. Post-bond test techniques for TSVs with crosstalk faults in 3D ICs
Lewis et al. Testing circuit-partitioned 3D IC designs
KR101643462B1 (en) Circuit and method for monolithic stacked integrated circuit testing
CN112595966A (en) IEEE standard based Chiplet circuit testing method
CN104205640B (en) Reconfigurable semiconductor device
Rajski et al. Fault diagnosis of TSV-based interconnects in 3-D stacked designs
Li et al. An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST
TW202324434A (en) A processor unit with combined memory, logic, and bist
Xie et al. Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs
Chou et al. A test integration methodology for 3D integrated circuits
Liu et al. BIST-diagnosis of interconnect fault locations in FPGA's
Pasca et al. Configurable thru-silicon-via interconnect built-in self-test and diagnosis
Taouil et al. Interconnect test for 3D stacked memory-on-logic
Hsu et al. Built-in test and diagnosis for TSVs with different placement topologies and crosstalk impact ranges
Hsu et al. 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults
Hu et al. Fault detection and redundancy design for TSVs in 3D ICs
Taouil et al. Exploring test opportunities for memory and interconnects in 3D ICs
Yang et al. A TSV repair scheme using enhanced test access architecture for 3-D ICs
Inoue et al. An easily testable routing architecture and efficient test technique
Tseng et al. A built-in method to repair SoC RAMs in parallel
Pasca et al. Csl: Configurable fault tolerant serial links for inter-die communication in 3d systems
WO2007143220A2 (en) Reconfigurable scan array structure