Nothing Special   »   [go: up one dir, main page]

Höppner et al., 2015 - Google Patents

An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS

Höppner et al., 2015

Document ID
15015245138110213340
Author
Höppner S
Walter D
Hocker T
Henker S
Hänzsche S
Sausner D
Ellguth G
Schlüßler J
Eisenreich H
Schüffny R
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long distance interconnects in the mm range within MPSoCs. Its source synchronous clocking scheme enables application in GALS systems and allows completely stoppable transceiver …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Similar Documents

Publication Publication Date Title
Krstic et al. Globally asynchronous, locally synchronous circuits: Overview and outlook
Höppner et al. An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS
Poulton et al. A 0.54 pJ/b 20 Gb/s ground-referenced single-ended short-reach serial link in 28 nm CMOS for advanced packaging applications
Ho et al. High speed and low energy capacitively driven on-chip wires
Fluhr et al. The 12-core power8™ processor with 7.6 tb/s io bandwidth, integrated voltage regulation, and resonant clocking
Walter et al. A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS
Dehlaghi et al. A 0.3 pJ/bit 20 Gb/s/wire parallel interface for die-to-die communication
Zhao et al. Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
US20130002300A1 (en) Serializing transmitter
Lee et al. Current-mode transceiver for silicon interposer channel
Lee et al. A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface
Dickson et al. A 1.8 pJ/bit $16\times 16\;\text {Gb/s} $ Source-synchronous parallel interface in 32 nm SOI CMOS with receiver redundancy for link recalibration
US9912337B2 (en) Systems and methods for configuring an SOPC without a need to use an external memory
US8497707B2 (en) Transmitter equalization method and circuit using unit-size and fractional-size subdrivers in output driver for high-speed serial interface
Chiu et al. A 65-nm 10-Gb/s 10-mm on-chip serial link featuring a digital-intensive time-based decision feedback equalizer
Bratov et al. Architecture and implementation of a low-power LVDS output buffer for high-speed applications
Yi et al. A 40 mV-differential-channel-swing transceiver using a RX current-integrating TIA and a TX pre-emphasis equalizer with a CML driver at 9 Gb/s
Sakthivel et al. MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture
Audzevich et al. Power optimized transceivers for future switched networks
Dazzi et al. Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes
Seo et al. Crosstalk-aware PWM-based on-chip links with self-calibration in 65 nm CMOS
Lee et al. A compact single-ended inverter-based transceiver with swing improvement for short-reach links
Teehan et al. Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Kumar et al. OpenSerDes: an open source process-portable all-digital serial link
Song et al. Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-$\mu\hbox {m} $ CMOS Technology