Szewczyk et al., 2000 - Google Patents
Energy implications of network sensor designsSzewczyk et al., 2000
View PDF- Document ID
- 14251869063083975791
- Author
- Szewczyk R
- Ferencz A
- Publication year
- Publication venue
- Berkeley Wireless Research Center Report
External Links
Snippet
Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world or spread throughout our environment. The fundamental …
- 238000004891 communication 0 abstract description 13
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
- Y02B60/10—Energy efficient computing
- Y02B60/16—Reducing energy-consumption in distributed systems
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
- Y02B60/10—Energy efficient computing
- Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
- Y02B60/1207—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
- Y02B60/1217—Frequency modification
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7788332B2 (en) | Sensor-network processors using event-driven architecture | |
US6959372B1 (en) | Processor cluster architecture and associated parallel processing methods | |
TWI502511B (en) | Resource management in a multicore architecture | |
Hill | A software architecture supporting networked sensors | |
EP2203811B1 (en) | Parallel processing computer system with reduced power consumption and method for providing the same | |
Szewczyk et al. | Energy implications of network sensor designs | |
Sabri et al. | Comparison of IoT constrained devices operating systems: A survey | |
Sutton et al. | Bolt: A stateful processor interconnect | |
WO2010046622A1 (en) | Integrated circuit incorporating an array of interconnected processors executing a cycle-based program | |
Paul et al. | Scenario-oriented design for single-chip heterogeneous multiprocessors | |
Madsen et al. | Network-on-chip modeling for system-level multiprocessor simulation | |
Riedy et al. | Power and control in networked sensors | |
Chen et al. | Hardware-modulated parallelism in chip multiprocessors | |
Wulf et al. | RTOS-supported low power scheduling of periodic hardware tasks in flash-based FPGAs | |
Ykman-Couvreur et al. | Design-time application exploration for MP-SoC customized run-time management | |
Chéour et al. | Exploitation of the EDF scheduling in the wireless sensors networks | |
Pezzarossa et al. | Reconfiguration in FPGA-based multi-core platforms for hard real-time applications | |
Madsen et al. | Abstract RTOS modeling for multiprocessor system-on-chip | |
Ventroux et al. | Scmp architecture: an asymmetric multiprocessor system-on-chip for dynamic applications | |
Peter | Resource management in a multicore operating system | |
Assayad et al. | Adaptive mapping for multiple applications on parallel architectures | |
Cheour et al. | Simulation of efficient real-time scheduling and power optimisation | |
Madsen et al. | Network-centric system-level model for multiprocessor soc simulation | |
D'amico | Scheduling and resource management solutions for the scalable and efficient design of today's and tomorrow's HPC machines | |
Virk et al. | A system-level multiprocessor system-on-chip modeling framework |