Zhu et al., 2018 - Google Patents
Improving first level cache efficiency for gpus using dynamic line protectionZhu et al., 2018
View PDF- Document ID
- 14246086637152548086
- Author
- Zhu X
- Wernsman R
- Zambreno J
- Publication year
- Publication venue
- Proceedings of the 47th International Conference on Parallel Processing
External Links
Snippet
A modern Graphics Processing Unit (GPU) utilizes L1 Data (L1D) caches to reduce memory bandwidth requirements and latencies. However, the L1D cache can easily be overwhelmed by many memory requests from GPU function units, which can bottleneck GPU performance …
- 230000002829 reduced 0 abstract description 3
Classifications
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
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