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Zhu et al., 2018 - Google Patents

Improving first level cache efficiency for gpus using dynamic line protection

Zhu et al., 2018

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Document ID
14246086637152548086
Author
Zhu X
Wernsman R
Zambreno J
Publication year
Publication venue
Proceedings of the 47th International Conference on Parallel Processing

External Links

Snippet

A modern Graphics Processing Unit (GPU) utilizes L1 Data (L1D) caches to reduce memory bandwidth requirements and latencies. However, the L1D cache can easily be overwhelmed by many memory requests from GPU function units, which can bottleneck GPU performance …
Continue reading at par.nsf.gov (PDF) (other versions)

Classifications

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    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
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    • G06F12/0893Caches characterised by their organisation or structure
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    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
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    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

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