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Xu et al., 2022 - Google Patents

HECTOR: A multi-level intermediate representation for hardware synthesis methodologies

Xu et al., 2022

Document ID
13720259089396538442
Author
Xu R
Xiao Y
Luo J
Liang Y
Publication year
Publication venue
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

External Links

Snippet

Hardware synthesis requires a complicated process to generate synthesizable register transfer level (RTL) code. High-level synthesis tools can automatically transform a high-level description into hardware design, while hardware generators adopt domain specific …
Continue reading at dl.acm.org (other versions)

Classifications

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