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하상원 et al., 2008 - Google Patents

Hierarchical Processing Architecture with Dynamically Allocated Nodes for 3D Graphics Shader

하상원 et al., 2008

Document ID
13405988830838550886
Author
하상원
정우남
한탁돈
Publication year
Publication venue
한국정보과학회 학술발표논문집

External Links

Snippet

Flexible programmability has become the key issue in polygon-based rasterization on 3D graphics hardware in endowing realism to the final image displayed. Yet, data parallelism must also be exploited in order to ensure performance at interactive rate. In this paper, a …
Continue reading at www.dbpia.co.kr (other versions)

Classifications

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    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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