Veloso et al., 2021 - Google Patents
Enabling logic with backside connectivity via n-TSVs and its potential as a scaling boosterVeloso et al., 2021
- Document ID
- 13324707351148342870
- Author
- Veloso A
- Jourdain A
- Hiblot G
- Schleicher F
- D’have K
- Sebaai F
- Radisic D
- Loo R
- Hopf T
- De Keersgieter A
- Arimura H
- Eneman G
- Favia P
- Geypen J
- Arutchelvan G
- Chasin A
- Jang D
- Nyns L
- Rosseel E
- Hikavyy A
- Mannaert G
- Chan B
- Devriendt K
- Demuynck S
- Van der Plas G
- Ryckaert J
- Beyer G
- Litta E
- Beyne E
- Horiguchi N
- Publication year
- Publication venue
- 2021 Symposium on VLSI Technology
External Links
Snippet
We report on scaled Si-channel finFETs (L gate> 20nm, 45nm fin pitch) with backside connectivity enabled by: extreme wafer thinning (several Si thicknesses under STI-oxide targeted: from~ 370nm down to~ 20nm) and W-filled nano-through-Si-vias (n-TSV) of …
- 230000015556 catabolic process 0 abstract description 7
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