Nothing Special   »   [go: up one dir, main page]

Giterman et al., 2017 - Google Patents

Hybrid GC-eDRAM/SRAM bitcell for robust low-power operation

Giterman et al., 2017

Document ID
13265153558777452514
Author
Giterman R
Teman A
Meinerzhagen P
Publication year
Publication venue
IEEE Transactions on Circuits and Systems II: Express Briefs

External Links

Snippet

Conventional static random access memory (SRAM) suffers from high leakage power when implemented in advanced CMOS nodes, while modified bitcells or assist techniques are required to achieve robust low-voltage operation. Gain-cell eDRAM (GC-eDRAM) is an …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • G11C11/419Read-write circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write (R-W) circuits
    • G11C11/4094Bit-line management or control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write (R-W) timing or clocking circuits; Read-write (R-W) control signal generators or management
    • G11C7/227Timing of memory operations based on dummy memory elements or replica circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06Sense amplifier related aspects
    • G11C2207/065Sense amplifier drivers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

Similar Documents

Publication Publication Date Title
Pasandi et al. An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs
Chun et al. A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches
Gupta et al. Pentavariate $ V_ {\mathrm {min}} $ Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read
Qazi et al. A 512kb 8T SRAM macro operating down to 0.57 V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45 nm SOI CMOS
Wang et al. Charge recycling 8T SRAM design for low voltage robust operation
Sharma et al. High performance process variations aware technique for sub-threshold 8T-SRAM cell
Panchal et al. Improved reliability single loop single feed 7T SRAM cell for biomedical applications
Siddiqui et al. A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI
Giterman et al. Hybrid GC-eDRAM/SRAM bitcell for robust low-power operation
Wang et al. A 4-kb low-power SRAM design with negative word-line scheme
Yang A low-power SRAM using bit-line charge-recycling for read and write operations
Mohammad et al. A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory
Lin et al. A highly-stable nanometer memory for low-power design
Wieckowski et al. Portless SRAM—a high-performance alternative to the 6T methodology
Golman et al. Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique
Akashe et al. Simulation and stability analysis of 6T and 9T SRAM cell in 45 nm era
Seyedzadeh Sany et al. A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications
Reddy et al. Sub-0.2 pJ/access Schmitt trigger based 1-kb 8T SRAM implemented using 40-nm CMOS process
Wang et al. Read bitline sensing and fast local write-back techniques in hierarchical bitline architecture for ultralow-voltage SRAMs
Apollos Design Principles of SRAM Memory in Nano-CMOS Technologies
Tawfik et al. Dynamic wordline voltage swing for low leakage and stable static memory banks
Yu et al. Single-port five-transistor SRAM cell with reduced leakage current in standby
Hsu et al. 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms
Harel et al. Replica bit-line technique for internal refresh in logic-compatible gain-cell embedded DRAM
Bhatnagar et al. A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation