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Pugsley et al., 2014 - Google Patents

Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers

Pugsley et al., 2014

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Document ID
12832433223523085239
Author
Pugsley S
Chishti Z
Wilkerson C
Chuang P
Scott R
Jaleel A
Lu S
Chow K
Balasubramonian R
Publication year
Publication venue
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

External Links

Snippet

Memory latency is a major factor in limiting CPU performance, and prefetching is a well- known method for hiding memory latency. Overly aggressive prefetching can waste scarce resources such as memory bandwidth and cache capacity, limiting or even hurting …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
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    • G—PHYSICS
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    • G06F11/3466—Performance evaluation by tracing or monitoring
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    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
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