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Hetherington et al., 1999 - Google Patents

Logic BIST for large industrial designs: Real issues and case studies

Hetherington et al., 1999

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Document ID
12653696311611309871
Author
Hetherington G
Fryars T
Tamarapalli N
Kassab M
Hassan A
Rajski J
Publication year
Publication venue
International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034)

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Snippet

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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    • G01R31/318555—Control logic
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    • G01R31/318572—Input/Output interfaces
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    • G01R31/318577—AC testing, e.g. current testing, burn-in
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    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G01R31/318583—Design for test
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