Nothing Special   »   [go: up one dir, main page]

Singh et al., 2014 - Google Patents

Knowledge-guided methodology for third-party soft ip analysis

Singh et al., 2014

View PDF
Document ID
12647408285938552368
Author
Singh B
Shankar A
Wolff F
Weyer D
Papachristou C
Negi B
Publication year
Publication venue
2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

External Links

Snippet

In System-on-Chip designs, third party IP reuse is prevalent as it increases productivity and reduces time-to-market. These IPs can be classified as untrusted designs since the user has no insight into IP verification or quality control process. In practice, it is generally assumed …
Continue reading at www.edautils.com (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3604Software analysis for verifying properties of programs
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/70Software maintenance or management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computer systems utilising knowledge based models
    • G06N5/02Knowledge representation
    • G06N5/022Knowledge engineering, knowledge acquisition
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management

Similar Documents

Publication Publication Date Title
CN109426722B (en) SQL injection defect detection method, system, equipment and storage medium
US10990725B2 (en) Clock-gating phase algebra for clock analysis
Kanewala et al. Predicting metamorphic relations for testing scientific software: a machine learning approach using graph kernels
US8181134B2 (en) Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design
US20040148150A1 (en) Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
Große et al. Quality-driven SystemC design
US8126831B2 (en) System and method for dynamically inferring data preconditions over predicates by tree learning
Letychevskyi et al. Modeling method for development of digital system algorithms based on programmable logic devices
Alizadeh et al. Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs
Salmani et al. Trusted Digital Circuits
Singh et al. Knowledge-guided methodology for third-party soft ip analysis
Lee et al. External don’t cares in logic synthesis
Guo et al. Automatic RTL-to-formal code converter for IP security formal verification
US6449752B1 (en) Digital circuit verification with automated specification enumeration
Ubar et al. Diagnostic modeling of digital systems with multi-level decision diagrams
Singh et al. Cross-correlation of specification and rtl for soft ip analysis
Hekmatpour et al. Block-based schema-driven assertion generation for functional verification
Brinkmann et al. Formal verification—the industrial perspective
US10546083B1 (en) System, method, and computer program product for improving coverage accuracy in formal verification
Raik et al. Code coverage analysis using high-level decision diagrams
Ehlers How Hard Is Finding Shortest Counter-Example Lassos in Model Checking?
US11507720B1 (en) Systems and methods for signal observability rating
Bao et al. A property language for the specification of hardware-dependent embedded system software
Chen et al. Automatic abstraction refinement for generalized symbolic trajectory evaluation
Jenihhin et al. High-level decision diagrams based coverage metrics for verification and test