Nothing Special   »   [go: up one dir, main page]

Feng et al., 2011 - Google Patents

Design and application of reusable SoC verification platform

Feng et al., 2011

Document ID
12226172260334347660
Author
Feng L
Dai Z
Li W
Cheng J
Publication year
Publication venue
2011 9th IEEE International Conference on ASIC

External Links

Snippet

This paper puts forward a kind of reusable SoC verification platform which reduces the complexity of SoC verification. The verification platform supports a mixed functional verification which includes both the IP core level and system level. All test program and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/86—Hardware-Software co-design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering

Similar Documents

Publication Publication Date Title
CN102508753B (en) IP (Internet protocol) core verification system
CN105205249B (en) A kind of SOC debugging verification systems and its software-hardware synergism method
US12093631B2 (en) Method, system and verifying platform for system on chip verification
US8214195B2 (en) Testing in a hardware emulation environment
CN102521444A (en) Cooperative simulation/verification method and device for software and hardware
CN113255267B (en) Reprogramming detection of timing violations in simulations using Field Programmable Gate Array (FPGA)
JP2007164780A (en) Method, system, and program (method and system of design verification)
Feng et al. Design and application of reusable SoC verification platform
Kang et al. Seamless SoC verification using virtual platforms: An industrial case study
US11023635B1 (en) Sequence of frames generated by emulation and waveform reconstruction using the sequence of frames
Gao et al. Software and hardware co-verification technology based on virtual prototyping of RF SOC
Ke et al. Verification of AMBA bus model using SystemVerilog
CN104679963A (en) Simulation and verification device and simulation and verification method based on TCL
Bombieri et al. Hybrid, incremental assertion-based verification for TLM design flows
Choi et al. Early HW/SW Co-Verification Using Virtual Platforms
CN106529043A (en) Method for carrying out sub-module comprehensive design on circuit on basis of computer software
US20220300690A1 (en) Incremental compilation for fpga-based systems
US12014205B2 (en) Advanced register merging
US20230071521A1 (en) Detecting simulation, emulation and prototyping issues using static analysis tools
CN113673106B (en) FPGA kernel programmable simulator
Lund Design and Application of a Co-Simulation Framework for Chisel
Lahbib et al. An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
US20240232485A1 (en) Test point insertion in analog circuit design testing
Lahbib et al. A new synchronization policy between PSL checkers and SystemC designs at transaction level
US20220382942A1 (en) Non-functional loopback-paths removal from io-pads using logic replication