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Tam et al., 1999 - Google Patents

Active management of data caches by exploiting reuse information

Tam et al., 1999

Document ID
12289696608450661741
Author
Tam E
Rivers J
Srinivasan V
Tyson G
Davidson E
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

As microprocessor speeds continue to outpace memory subsystems in speed, minimizing average data access time grows in importance. Multilateral caches afford an opportunity to reduce the average data access time by active management of block allocation and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • G—PHYSICS
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    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
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    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G06F9/3824—Operand accessing
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    • G06F9/46—Multiprogramming arrangements
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    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching
    • G—PHYSICS
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    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

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