Nothing Special   »   [go: up one dir, main page]

Bhattacharjee et al., 2017 - Google Patents

A 23.52 µW/0.7 V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock

Bhattacharjee et al., 2017

View PDF
Document ID
10866015349990749985
Author
Bhattacharjee P
Majumder A
Nath B
Publication year
Publication venue
IEIE Transactions on Smart Processing and Computing

External Links

Snippet

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of …
Continue reading at koreascience.kr (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass

Similar Documents

Publication Publication Date Title
Kong et al. Conditional-capture flip-flop for statistical power reduction
Gupta et al. Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells
Sharma et al. Modified SET D-flip flop design for low-power VLSI applications
Sharma et al. An area and power efficient design of single edge triggered D-flip flop
Bhattacharjee et al. A 23.52 µW/0.7 V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock
Bhattacharjee et al. A variation-aware robust gated flip-flop for power-constrained FSM application
Khan et al. 2 GHz low power double edge triggered flip-flop in 65nm CMOS technology
Balaji et al. Low power and high speed synchronous circuits using transmission gates
Katreepalli et al. Energy-efficient synchronous counter design with minimum hardware overhead
Maiti et al. A Dynamic Current Mode D-Flipflop for High Speed Application
Sharma et al. SET D-flip flop design for portable applications
Khan et al. Analysis of different techniques for low power Single Edge Triggered Flip Flops
Nagarajan et al. Efficient timing element design featuring low power vlsi application
Rasouli et al. Double edge triggered feedback flip-flop in sub 100nm technology
Noble et al. A novel flip-flop design for low power clocking system
Kumar et al. Implementation of High Performance Clock-gated Flip-flops
Abhishek et al. Low Power DET Flip-Flops Using C-Element
Bikki et al. Analysis of low power feed through logic with leakage control technique
Srividya Finfet based Frequency Divider Design Using True Single Phase Clock Technique
Agrawal et al. Implementation of PFSCL razor flipflop
Saw et al. Design and implementation of TG based D flip flop for clock and data recovery application
Pandey et al. Implementation of Low-Power Frequency Divider Circuit using GDI Technique
Kiran et al. A Conditional Feedthrough Pulsed Flip-Flop using MTCMOS Technique
Agarwal et al. Comparative analysis of low power high performance flip–flops in the 0.13 µm technology
Kassa et al. Forced stack sleep transistor (FORTRAN): a new leakage current reduction approach in CMOS based circuit designing