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Lin et al., 2001 - Google Patents

Designing a modern memory hierarchy with hardware prefetching

Lin et al., 2001

Document ID
10132792158376157137
Author
Lin W
Reinhardt S
Burger D
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

In this paper, we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that, even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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