Nothing Special   »   [go: up one dir, main page]

Ma et al., 2013 - Google Patents

Design of a delay-locked-loop-based time-to-digital converter

Ma et al., 2013

Document ID
9920235482823842951
Author
Ma Z
Bai X
Huang L
Publication year
Publication venue
Journal of Semiconductors

External Links

Snippet

A time-to-digital converter (TDC) based on a reset-free and anti-harmonic delay-locked loop (DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid" false locking" …
Continue reading at iopscience.iop.org (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass

Similar Documents

Publication Publication Date Title
Yang et al. A 2.5 GHz All-Digital Delay-Locked Loop in 0.13$\mu {\hbox {m}} $ CMOS Technology
Lu et al. A 2.2-ps two-dimensional gated-Vernier time-to-digital converter with digital calibration
Liu et al. A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO
Lee et al. A 0.3-to-1.2 V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC
Nguyen et al. Three-step cyclic Vernier TDC using a pulse-shrinking inverter-assisted residue quantizer for low-complexity resolution enhancement
Tao et al. An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and–252 dB FoM
Liang et al. An all-digital fast-locking programmable DLL-based clock generator
Yuan CMOS time‐to‐digital converters for mixed‐mode signal processing
Ma et al. Design of a delay-locked-loop-based time-to-digital converter
Jiang et al. A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology
Sahani et al. A wide frequency range low jitter integer PLL with switch and inverter based CP in 0.18 μ m CMOS technology
Zhang et al. A fast-locking digital DLL with a high resolution time-to-digital converter
Goyal et al. Design of charge pump PLL using improved performance ring VCO
Jung et al. All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate
Ryu et al. All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate
Nakura et al. Low pass filter-less pulse width controlled PLL using time to soft thermometer code converter
Annagrebah et al. A multi-phase time-to-digital converter differential vernier ring oscillator
Wu et al. A hybrid time-to-digital converter based on residual time extraction and amplification
Li et al. A fast locking-in and low jitter PLLWith a process-immune locking-in monitor
Cheng et al. A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop
Yang et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits
Mondal et al. Fast locking, startup-circuit free, low area, 32-phase analog DLL
Bayat et al. Low-power Time-to-Digital Converter Based on Vernier Gated-Ring-Oscillator
Wang et al. A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC
Khan et al. All-Digital Delay-Locked Loop-based Frequency Multiplier Operating from 4.0 GHz to 5.6 GHz