Nothing Special   »   [go: up one dir, main page]

Kayssi et al., 1993 - Google Patents

The impact of signal transition time on path delay computation

Kayssi et al., 1993

View PDF
Document ID
9715163581894438560
Author
Kayssi A
Sakallah K
Mudge T
Publication year
Publication venue
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

External Links

Snippet

It has been recognized for some time that nonzero signal rise and fall times contribute to gate propagation delays. Practically, however, most timing analysis tools ignore these contributions when computing path delays and identifying critical paths in combinational …
Continue reading at tnm.engin.umich.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
Kayssi et al. The impact of signal transition time on path delay computation
US7428716B2 (en) System and method for statistical timing analysis of digital circuits
US6158022A (en) Circuit analyzer of black, gray and transparent elements
US7086023B2 (en) System and method for probabilistic criticality prediction of digital circuits
US6615395B1 (en) Method for handling coupling effects in static timing analysis
US6499129B1 (en) Method of estimating performance of integrated circuit designs
US5751593A (en) Accurate delay prediction based on multi-model analysis
US7340698B1 (en) Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components
US6212665B1 (en) Efficient power analysis method for logic cells with many output switchings
US6651229B2 (en) Generation of refined switching windows in static timing analysis
US5790415A (en) Complementary network reduction for load modeling
Chandramouli et al. Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time
US5787008A (en) Simulation corrected sensitivity
US8056035B2 (en) Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing
US5636130A (en) Method of determining signal propagation delay through circuit elements
EP1192569A1 (en) Circuit simulation using dynamic partitioning and on-demand evaluation
US20030061573A1 (en) Method and program for supporting register-transfer-level design of semiconductor integrated circuit
Ramesh et al. Artificial neural network model for arrival time computation in gate level circuits
KR100482894B1 (en) How to Optimize Device Sizes in Semiconductor Devices
Chakraborty et al. More accurate polynomial-time min-max timing simulation
Tseng et al. Static noise analysis with noise windows
McMurchie et al. WTA: waveform-based timing analysis for deep submicron circuits
Raja et al. A reduced constraint set linear program for low-power design of digital circuits
Yalcin et al. Functional timing analysis for IP characterization
US6990643B1 (en) Method and apparatus for determining whether an element in an integrated circuit is a feedback element