Nothing Special   »   [go: up one dir, main page]

Tong et al., 2007 - Google Patents

Wire retiming problem with net topology optimization

Tong et al., 2007

View PDF
Document ID
9303724111372773606
Author
Tong D
Young E
Chu C
Dechu S
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

In this paper, we study the retiming problem of sequential circuits with net topology optimization. Both interconnect and gate delay are considered in retiming. Most previous retiming algorithms have assumed ideal conditions for the nonlogical portions of data paths …
Continue reading at class.ece.iastate.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformations of program code
    • G06F8/41Compilation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F19/00Digital computing or data processing equipment or methods, specially adapted for specific applications
    • G06F19/10Bioinformatics, i.e. methods or systems for genetic or protein-related data processing in computational molecular biology
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence

Similar Documents

Publication Publication Date Title
Schafer et al. High-level synthesis design space exploration: Past, present, and future
US6415430B1 (en) Method and apparatus for SAT solver architecture with very low synthesis and layout overhead
Eles et al. System synthesis with VHDL
US6378123B1 (en) Method of handling macro components in circuit design synthesis
US6763506B1 (en) Method of optimizing the design of electronic systems having multiple timing constraints
US6782511B1 (en) Behavioral-synthesis electronic design automation tool business-to-business application service provider
Zheng et al. High-level synthesis with behavioral-level multicycle path analysis
Ansaloni et al. Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays
Stroele et al. Hardware-optimal test register insertion
Knapp Fasolt: A program for feedback-driven data-path optimization
JP4495865B2 (en) Inter-trade application service provider
Zhong et al. FPGA-based SAT solver architecture with near-zero synthesis and layout overhead
Vahid et al. Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
Karmazin et al. Timing driven placement for quasi delay-insensitive circuits
Chu et al. Retiming with interconnect and gate delay
Hoskote et al. Automatic verification of implementations of large circuits against HDL specifications
US6516453B1 (en) Method for timing analysis during automatic scheduling of operations in the high-level synthesis of digital systems
Nourani et al. False path exclusion in delay analysis of RTL structures
Tong et al. Wire retiming problem with net topology optimization
Chen et al. Simultaneous placement with clustering and duplication
Wu et al. Further improve circuit partitioning using GBAW logic perturbation techniques
Lin et al. Optimal wire retiming without binary search
Jantsch et al. Models of computation in the design process
Roy The use of RTL descriptions in accurate timing verification and test generation (VLSI)
Tong et al. Performance-driven register insertion in placement