Nothing Special   »   [go: up one dir, main page]

Kuroda et al., 1996 - Google Patents

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Kuroda et al., 1996

Document ID
8446207212567974200
Author
Kuroda T
Fujita T
Mita S
Nagamatsu T
Yoshioka S
Suzuki K
Sano F
Norishima M
Murota M
Kako M
Kinugawa M
Kakumu M
Sakurai T
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures

Similar Documents

Publication Publication Date Title
Kuroda et al. A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
Agarwal et al. Leakage power analysis and reduction for nanoscale circuits
Paul et al. Low-power design techniques for scaled technologies
Kim et al. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
Mai et al. Low-power SRAM design using half-swing pulse-mode techniques
Henzler Power management of digital circuits in deep sub-micron CMOS technologies
Mizuno et al. An 18-/spl mu/A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
US7342287B2 (en) Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures
Enomoto et al. A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
Kuroda et al. A high-speed low-power 0.3/spl mu/m CMOS gate array with variable threshold voltage (VT) scheme
Won et al. An MTCMOS design methodology and its application to mobile computing
Birla et al. Device and circuit design challenges for low leakage SRAM for ultra low power applications
Tsai et al. Characterization and modeling of run-time techniques for leakage power reduction
Ishibashi et al. A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode
Puri et al. Keeping hot chips cool
Kuroda Low-power, high-speed CMOS VLSI design
Kuroda et al. Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design
Kuroda Low power CMOS digital design for multimedia processors
Narayan et al. A novel sleepy stack 6-T SRAM cell design for reducing leakage power in submicron technologies
Shukla et al. A novel approach to reduce the gate and sub-threshold leakage in a conventional SRAM bit-cell structure at deep-sub micron CMOS technology
Kuroda et al. Variable threshold-voltage CMOS technology
Kumar et al. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage
Singh et al. Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells
Roy et al. Leakage control for deep-submicron circuits
Kakumu et al. Tadahiro Kuroda, Member, IEEE, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Member, IEEE