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Xu et al., 2003 - Google Patents

Advanced topics of DFT technologies in a general purposed CPU chip

Xu et al., 2003

Document ID
7522706859334502525
Author
Xu Y
Lv T
Lu W
Yang X
Li H
Li X
Publication year
Publication venue
2003 5th International Conference on ASIC Proceedings

External Links

Snippet

Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any functional influence. How to make all the …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
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    • G01R31/318572—Input/Output interfaces
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    • G—PHYSICS
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    • G—PHYSICS
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    • G01R33/00—Arrangements or instruments for measuring magnetic variables

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