Barik et al., 2017 - Google Patents
Efficient ASIC and FPGA implementation of cube architectureBarik et al., 2017
View PDF- Document ID
- 7342282029706732306
- Author
- Barik R
- Pradhan M
- Publication year
- Publication venue
- IET computers & digital techniques
External Links
Snippet
This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers …
- 238000003786 synthesis reaction 0 abstract description 11
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/20—Handling natural language data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Labrado et al. | Design of adder and subtractor circuits in majority logic‐based field‐coupled QCA nanocomputing | |
Barik et al. | Efficient ASIC and FPGA implementation of cube architecture | |
Sasamal et al. | Design of non‐restoring binary array divider in majority logic‐based QCA | |
Xue et al. | Low‐power‐delay‐product radix‐4 8* 8 Booth multiplier in CMOS | |
Barik et al. | Time efficient signed Vedic multiplier using redundant binary representation | |
Abed et al. | Low power Wallace multiplier design based on wide counters | |
Liacha et al. | Design of high‐speed, low‐power, and area‐efficient FIR filters | |
Leon et al. | Energy‐efficient VLSI implementation of multipliers with double LSB operands | |
Palanisamy et al. | Area‐efficient parallel adder with faithful approximation for image and signal processing applications | |
Sahu et al. | Fast signed multiplier using Vedic Nikhilam algorithm | |
Fatemi et al. | Efficient implementation of digit‐serial Montgomery modular multiplier architecture | |
Hiasat | Sign detector for the extended four‐moduli set | |
Das et al. | FPGA and ASIC realisation of EMD algorithm for real‐time signal processing | |
Patel et al. | Area–delay and energy efficient multi‐operand binary tree adder | |
Niras et al. | Fast sign‐detection algorithm for residue number system moduli set {2n− 1, 2n, 2n+ 1− 1} | |
Chen | High‐order Taylor series approximation for efficient computation of elementary functions | |
Cui et al. | Design of non‐restoring binary array divider in quantum‐dot cellular automata | |
Banerjee et al. | A New Squarer design with reduced area and delay | |
Shirol et al. | Design and implementation of adders and multiplier in FPGA using Chipscope: a performance improvement | |
Huang et al. | Approximate computing using frequency upscaling | |
Saini et al. | Implementation, test pattern generation, and comparative analysis of different adder circuits | |
Parhami | Truncated ternary multipliers | |
Kaivani et al. | Area efficient floating‐point FFT butterfly architectures based on multi‐operand adders | |
Almatrood et al. | QCA circuit design of n‐bit non‐restoring binary array divider | |
Tomar et al. | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |