Warwick, 2002 - Google Patents
What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit regionWarwick, 2002
View PDF- Document ID
- 6932002475283457687
- Author
- Warwick T
- Publication year
- Publication venue
- Proceedings. International Test Conference
External Links
Snippet
The purpose of this paper is to explore the causes of measurement error relating to the device interface board (DIB or DUT (device under test) board) in both ATE and bench characterization for devices operating over 1 Gigabit. Nearly all test setups for high-speed …
- 238000011156 evaluation 0 title description 3
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, and noise or electromagnetic interference
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6917210B2 (en) | Integrated circuit tester with high bandwidth probe assembly | |
US7203460B2 (en) | Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit | |
US20160065334A1 (en) | Structure and Implementation Method for implementing an embedded serial data test loopback, residing directly under the device within a printed circuit board | |
US20010002794A1 (en) | Split resistor probe and method | |
Warwick | What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit region | |
Carlton et al. | Accurate measurement of high-speed package and interconnect parasitics | |
Montrose | EMC and printed circuit board design | |
EP2684063B1 (en) | Non-contact testing devices for printed circuit boards transporting high-speed signals | |
Huang et al. | Investigation of signal integrity issues in multi-path electrostatic discharge protection device | |
Anish et al. | Minimization of crosstalk in high speed PCB | |
Lacrampe et al. | Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester | |
Huang et al. | Probe with absorbing materials | |
Gong et al. | Investigation of high-speed pulse transmission in MCM-D | |
Budell et al. | Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16/spl mu/m CMOS test chip | |
Song et al. | Probe Card Design with Signal and Power Integrity for Wafer-Level Application Processor Test in LPDDR Channel | |
US8024679B2 (en) | Structure for apparatus for reduced loading of signal transmission elements | |
Van Hauwermeiren et al. | Characterization and modeling of packages by a time-domain reflectometry approach | |
Musolino et al. | Investigation on the susceptibility of microcontrollers to EFT interference | |
Dattaprasad et al. | Signal integrity factors in high speed multi-board test setup | |
Agarwal et al. | Application of Signal Processing Techniques for Noise Reduction | |
Pointl | Interfacing, often a performance bottleneck between ATE and device under test | |
Sarkar | Jestr r | |
Nakayama et al. | Proposal of a current measurement technique for each pin of a BGA package | |
Sarkar | A Simple and Noble Technique for Signal Integrity Test. | |
Cocovich | Emi/rfi board design |