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Chakraborty et al., 2017 - Google Patents

Matching multiplications in bit-vector formulas

Chakraborty et al., 2017

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Document ID
6883395925456483703
Author
Chakraborty S
Gupta A
Jain R
Publication year
Publication venue
Verification, Model Checking, and Abstract Interpretation: 18th International Conference, VMCAI 2017, Paris, France, January 15–17, 2017, Proceedings 18

External Links

Snippet

Bit-vector formulas arising from hardware verification problems often contain word-level arithmetic operations. Empirical evidence shows that state-of-the-art SMT solvers are not very efficient at reasoning about bit-vector formulas with multiplication. This is particularly …
Continue reading at arxiv.org (PDF) (other versions)

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