Ghosh et al., 2019 - Google Patents
Case Study: SoC Performance Verification and Static Verification of RTL ParametersGhosh et al., 2019
- Document ID
- 6690046305564711443
- Author
- Ghosh P
- Rohit S
- Publication year
- Publication venue
- 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV)
External Links
Snippet
Modern SoCs are developed by integrating several hundreds of IPs like hardware accelerators, I/O interfaces, memories, controllers, third party IPs, etc. It mostly uses several interconnects or cache coherent network for integration. Such complicated SoCs are prone …
- 230000003068 static 0 title description 6
Classifications
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- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- G06F17/504—Formal methods
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- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
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- G—PHYSICS
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- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
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