Nothing Special   »   [go: up one dir, main page]

Lu et al., 2021 - Google Patents

NeuroSim validation with 40nm RRAM compute-in-memory macro

Lu et al., 2021

Document ID
6331609521375185057
Author
Lu A
Peng X
Li W
Jiang H
Yu S
Publication year
Publication venue
2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)

External Links

Snippet

Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models
    • G06N3/02—Computer systems based on biological models using neural network models
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistance random access memory [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models
    • G06N3/12—Computer systems based on biological models using genetic models
    • G06N3/126—Genetic algorithms, i.e. information processing using digital simulations of the genetic system

Similar Documents

Publication Publication Date Title
Lu et al. NeuroSim simulator for compute-in-memory hardware accelerator: Validation and benchmark
Peng et al. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training
Sinangil et al. A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS
Lu et al. NeuroSim validation with 40nm RRAM compute-in-memory macro
Yu et al. RRAM for compute-in-memory: From inference to training
Peng et al. DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies
Kim et al. Colonnade: A reconfigurable SRAM-based digital bit-serial compute-in-memory macro for processing neural networks
Yu et al. Compute-in-memory chips for deep learning: Recent trends and prospects
Xia et al. MNSIM: Simulation platform for memristor-based neuromorphic computing system
Yang et al. Research progress on memristor: From synapses to computing systems
Verma et al. In-memory computing: Advances and prospects
Murmann Mixed-signal computing for deep neural network inference
Chen et al. NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
Roy et al. In-memory computing in emerging memory technologies for machine learning: An overview
Talati et al. Logic design within memristive memories using memristor-aided loGIC (MAGIC)
Giacomin et al. A robust digital RRAM-based convolutional block for low-power image processing and learning applications
Staudigl et al. A survey of neuromorphic computing-in-memory: Architectures, simulators, and security
Murali et al. Heterogeneous mixed-signal monolithic 3-D in-memory computing using resistive RAM
Zhang et al. PIMCA: A programmable in-memory computing accelerator for energy-efficient DNN inference
Zidan et al. Field-programmable crossbar array (FPCA) for reconfigurable computing
Gebregiorgis et al. Tutorial on memristor-based computing for smart edge applications
Jing et al. VSDCA: A voltage sensing differential column architecture based on 1T2R RRAM array for computing-in-memory accelerators
Taylor et al. Processing-in-memory technology for machine learning: From basic to asic
Li et al. H3datten: Heterogeneous 3-d integrated hybrid analog and digital compute-in-memory accelerator for vision transformer self-attention
Krestinskaya et al. Towards efficient in-memory computing hardware for quantized neural networks: state-of-the-art, open challenges and perspectives