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Fujisawa et al., 2017 - Google Patents

A software implementation of speculative memory

Fujisawa et al., 2017

Document ID
4715134273978331169
Author
Fujisawa K
Nunome A
Shibayama K
Hirata H
Publication year
Publication venue
2017 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)

External Links

Snippet

Many techniques for parallelizing a sequentially coded program have been developed and put to practical use, but there are many cases in which program codes cannot be parallelized because it is impossible to assure that their parallel execution does not violate …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F9/30003—Arrangements for executing specific machine instructions
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    • G06F9/30087—Synchronisation or serialisation instructions
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    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
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