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Abrokwah et al., 1993 - Google Patents

A manufacturable complementary GaAs process

Abrokwah et al., 1993

Document ID
4702234990846274538
Author
Abrokwah J
Huang J
Ooms W
Shurboff C
Hallmark J
Lucero R
Gilbert J
Bernhards B
Hansell G
Publication year
Publication venue
15th Annual GaAs IC Symposium

External Links

Snippet

A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process …
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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