Li et al., 2015 - Google Patents
Wafer-level wet etching of high-aspect-ratio through silicon vias (TSVs) with high uniformity and low cost for silicon interposers with high-density interconnect of 3D …Li et al., 2015
View PDF- Document ID
- 4269730644161081513
- Author
- Li L
- Wu J
- Wong C
- Publication year
- Publication venue
- 2015 IEEE 65th Electronic Components and Technology Conference (ECTC)
External Links
Snippet
Silicon (Si) interposers have received an increasing amount of attention in microelectronic packaging industry due to its potential application in the emerging 2.5 D system integration. One of the key steps in the fabrication flow of Si interposer is the formation of through silicon …
- 229910052710 silicon 0 title abstract description 28
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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