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A Low-Energy and Area-Efficient Vaq-Based Switching Scheme with Capacitor-Splitting Structure for SAR ADCs

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Abstract

A novel energy-saving and area-efficient tri-level switching scheme is proposed for successive approximation register analog-to-digital converters (SAR ADCs). Different from most published tri-level switching schemes, a new third reference voltage Vaq which equals to 1/4 Vref is applied to the proposed scheme. And benefiting from Vaq, the proposed scheme achieves 87.5% capacitor area reduction over the conventional scheme. Due to the capacitor-splitting structure and top-plate sampling, the switching energy is negative during the first three switching cycles, which means the capacitor arrays return energy back to the reference voltages and results in significant energy saving. For a 10-bit SAR ADC, the average switching energy of proposed scheme is only 5.3 \(CV_{{{\text{ref}}}}^{2}\), which realizes 99.61% energy saving compared with the conventional scheme. Moreover, the proposed scheme is of low control logic complexity since single-side switching is applied during the remaining switching cycles. Therefore, the proposed scheme achieves a good trade-off among energy saving, area efficiency and logic complexity. For a 10-bit SAR ADC, the simulated differential nonlinearity (DNL) and integral nonlinearity (INL) with 1% capacitor mismatch are 0.322 LSB and 0.321 LSB, respectively. Considering 0.3% reference voltage mismatch, the mean values of effective number of bits (ENOB), signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) are 9.77 bit, 60.57 dB and 75.43 dB, respectively, through 500 Monte Carlo simulations. To verify the feasibility of circuit implementation, transistor level simulation of a 0.6-V 10-bit 200-KS/s SAR ADC in 40-nm CMOS technology is performed. The ENOB, SNDR and SFDR of SAR ADC with 98.83-kHz Nyquist rate input are 9.66 bit, 59.90 dB and 71.98 dB, respectively.

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The processed data and material required to reproduce these findings cannot be shared at this time as the data also forms part of an ongoing study.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (No. 61871118), the Fundamental Research Funds for the Central Universities (No. 2242019k30037) and the Top-notch Academic Programs Project of Jiangsu Higher Education Institutions (TAPP) (No. PPZY2015B136).

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Authors and Affiliations

  1. National ASIC Research Center, Southeast University, Nanjing, 210096, Jiangsu, China

    Linlin Huang, Lizhen Zhang, Minggang Chen, Junhui Li & Jianhui Wu

  2. Jiangsu Provincial Key Laboratory of Sensor Network Technology, Southeast University, Nanjing, 210096, Jiangsu, China

    Linlin Huang, Lizhen Zhang, Junhui Li & Jianhui Wu

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  1. Linlin Huang
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  2. Lizhen Zhang
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Correspondence to Jianhui Wu.

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Huang, L., Zhang, L., Chen, M. et al. A Low-Energy and Area-Efficient Vaq-Based Switching Scheme with Capacitor-Splitting Structure for SAR ADCs. Circuits Syst Signal Process 40, 4106–4126 (2021). https://doi.org/10.1007/s00034-021-01666-0

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