Abstract: An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup ...

This paper describes an experimental 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM obtained by applying these novel circuit techniques featuring an ECL high-speed ...

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory ...

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory ...

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory ...

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-μm MOS ...

An ultra-high-speed 1 Mb ECL-CMOS SRAM with 550 ps access time and 900 MHz ... A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram. Citing Conference Paper.

A 0.65-ns, 72-kb ecl-cmos ram macro for a 1-mb sram. In IEEE J. Solid-State ... A 16-mb 400-mhz loadless cmos four transistor sram macro. In IEEE J ...

TL;DR: In this paper, an ultrahigh speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65ns address-access time, 0.80ns write-pulse width, and 30.24-/spl mu/m ...

Apr 25, 2024 · A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. IEEE J. Solid State Circuits 30(4): 491-499 (1995); 1994. [j1]. view. electronic edition ...