Heap sort in hardware

See performance table here.

Create a new file with test values

make test-files/<file-name>.txt N=? W=?

Emit verilog RTL

make gen K=? W=? TEST_FILE=test-files/<file-name>.txt

Verilog RTL is placed in /build.

Run Xilinx Vivado synthesis for Basys3

make synth K=? W=? TEST_FILE=test-files/<file-name>.txt

Utilization and timing analysis reports are placed in /build

Program Basys3

make download K=? W=? TEST_FILE=test-files/<file-name>.txt

Run RTL tests

make rtl-test

Performance

Create performance table for different sizes and tree orders:

make performance-table

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
doc		doc
energy		energy
src		src
test-files		test-files
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
build.sbt		build.sbt
heap-sort-performance.csv		heap-sort-performance.csv
heap-sort-power.csv		heap-sort-power.csv
pinout.xdc		pinout.xdc
timing.tcl		timing.tcl

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Heap sort in hardware

Create a new file with test values

Emit verilog RTL

Run Xilinx Vivado synthesis for Basys3

Program Basys3

Run RTL tests

Performance

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Heap sort in hardware

Create a new file with test values

Emit verilog RTL

Run Xilinx Vivado synthesis for Basys3

Program Basys3

Run RTL tests

Performance

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