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This is the top-level repository for the Accel-Sim framework.
A machine learning accelerator core designed for energy-efficient AI at the edge.
Strided Data Prefetcher for High-Performance Cache Hierarchies
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
GNU toolchain for RISC-V, including GCC
FSA: Fusing FlashAttention within a Single Systolic Array
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It should be regarded as an onward work for FlexGrip Plus
Fast and memory-efficient exact attention
Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.
Contains the code examples from The UVM Primer Book sorted by chapters.
Functional verification project for the CORE-V family of RISC-V cores.
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Open-source high-performance RISC-V processor