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8000 liuyic00 (Yicheng Liu) · GitHub
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  • Institute of Software Chinese Academy of Sciences
  • Beijing, China
  • 19:50 (UTC +08:00)

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  1. iscas-tis/chicala iscas-tis/chicala Public

    Translate Chisel hardware design code to Scala simulation code.

    Scala 10 1

  2. iscas-tis/ChiRVFormal iscas-tis/ChiRVFormal Public

    Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.

    Scala 14 8

0