A Verilog implementation of a processor cache.

A machine learning accelerator core designed for energy-efficient AI at the edge.

Quasar 2.0: Chisel equivalent of SweRV-EL2

Open source high performance IEEE-754 floating unit

System verilog support VS Code Extension

Tools based upon slang for language server purpose

A SystemVerilog language server based on the Slang library.

Jaxpr Visualisation Tool

A model context protocol server for solving combinatorial optimization problems with logical and numerical constraints.

Model Context Protocol (MCP) implementation in Rust

Lean Theorem Prover MCP

Packed data structure specifications for multi-language hardware projects.

Experimental Chisel g8 Template

The user home repository for the Mathematics in Lean tutorial.

An implementation of RISC-V

APyTypes - Algorithmic data types for Python

Test designs for various primitives supported by openXC7

Chisel RISC-V Vector 1.0 Implementation

Macros for all your token pasting needs. Successor of paste

An open-source library of metrics for side-channel analysis

This repository contains SystemVerilog code of the masked X2X (A2B & B2A) accelerator for lattice-based cryptography.

Hardware generator debugger

Test of generated ROM macros

Plotly for Rust