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1. dclab_final dclab_final Public

   Tank Game implementation on FPGA

   SystemVerilog 1

2. Electrical-Engineering-Lab---networking-and-Multinmedia Electrical-Engineering-Lab---networking-and-Multinmedia Public

   Final project of networking and Multinmedia

   Jupyter Notebook 1

3. Fraig Fraig Public

   Functionally Reduced And-Inverter Graph (FRAIG)

   C++ 1

4. Image_Convolutional_Circuit_Design Image_Convolutional_Circuit_Design Public

   Final project of Integrated Circuit Design in 2019 Spring

   Verilog

5. Smith_Waterman_Hardware_Implementation Smith_Waterman_Hardware_Implementation Public

   Bachelor project from the professor Yi-Chang Lu in NTUEE

   Verilog

6. web_learning web_learning Public

   Self learning about web

   Python