A machine learning accelerator core designed for energy-efficient AI at the edge.

VHDL compiler and simulator

general-cores

HDL libraries and projects

LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

GHDL VUnit + UVVM + OSVVM Template

This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from Cologne Chip

Hardware Design, Exploration, and Code Generation for SoC Designers

Open source RTL simulation acceleration on commodity hardware

Making cocotb testbenches that bit easier

VHDL generator from SystemRDL

Playing around with Formal Verification of Verilog and VHDL

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

Open Logic FPGA Standard Library

Python/C/RTL cosimulation with Xilinx's xsim simulator

An open-source HDL register code generator fast enough to run in real time.

A simple makefile for C and C++ projects.