Stars
A Fully Open-Source Verilog-to-PCB Flow
The central registry of Bazel modules for the Bzlmod external dependency system.
An experimental Clinical Quality Language execution engine for analyzing FHIR healthcare data at scale.
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging
Kokkos C++ Performance Portability Programming Ecosystem: The Programming Model - Parallel Execution and Memory Abstraction
ABC: System for Sequential Logic Synthesis and Formal Verification
Generic Process Design Kit for Gdsfactory
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
fakeram generator for use by researchers who do not have access to commercial ram generators
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
A simple MOSFET model with only 5-DC-parameters for circuit simulation
Experiments in understanding PCIe topology of my Supermicro servers....
Modern VNC Server and client, web based and secure
Plugins for Yosys developed as part of the F4PGA project.
Practical mutation testing and fault injection for C and C++
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design